1. Field of the Invention
The present invention relates generally to methods for forming trench fill layers within trenches within substrates employed within microelectronics fabrications. More particularly, the present invention relates to methods for forming with attenuated substrate surface erosion chemical mechanical polish (CMP) planarized trench fill layers within trenches within substrates employed within microelectronics fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronics fabrications are formed from semiconductor substrates within and upon which are formed integrated circuit devices. The integrated circuit devices are connected internally and externally to the semiconductor substrates upon which they are formed while employing patterned integrated circuit conductor layers which are separated by integrated circuit dielectric layers.
As integrated circuit microelectronics fabrication integration levels have increased and integrated circuit device and patterned conductor layer dimensions have decreased, it has become more prevalent within the art of integrated circuit microelectronics fabrication to employ trench isolation methods, such as but not limited to shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods, to form trench isolation regions within a semiconductor substrate in order to separate active regions of the semiconductor substrate within and upon which are formed integrated circuit devices.
Such shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are desirable within integrated circuit microelectronics fabrications since shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods provide trench isolation regions which are nominally co-planar with a surface of an adjoining active region of a semiconductor substrate. Such nominally co-planar trench isolation regions and adjoining active regions of a semiconductor substrate generally optimize an attenuated depth of focus typically achievable with an advanced photoexposure apparatus employed when forming advanced integrated circuit microelectronics devices and advanced patterned conductor layers within an advanced integrated circuit microelectronics fabrication.
While shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are thus desirable when forming trench isolation regions within advanced integrated circuit microelectronics fabrications, shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods are nonetheless not formed entirely without problems within advanced integrated circuit microelectronics fabrications. In particular, it is often difficult to form when employing shallow trench isolation (STI) methods within integrated circuit microelectronics fabrications shallow trench isolation (STI) regions which simultaneously possess superior gap filling properties, superior bulk physical properties and enhanced deposition rates which in the aggregate provide shallow trench isolation regions with optimal properties within advanced integrated circuit microelectronics fabrications.
Of the dielectric layer deposition methods potentially applicable for forming shallow trench isolation regions when employing shallow trench isolation (STI) methods within integrated circuit microelectronics fabrications, atmospheric pressure thermal chemical vapor deposition (APCVD) methods and sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods employing ozone as an oxidant source material and tetraethylorthosilicate (TEOS) as a silicon source material (hereinafter, in general, "ozone-TEOS thermal chemical vapor deposition (CVD) methods") are particularly desirable due to the superior gap filling properties of shallow trench isolation regions formed employing those ozone-TEOS thermal chemical vapor deposition (CVD) methods. Such ozone-TEOS thermal chemical vapor deposition (CVD) methods typically preclude plasma activation due to the increased reactor chamber pressures at which they are undertaken. While ozone-TEOS thermal chemical vapor deposition (CVD) methods do typically provide shallow trench isolation regions formed with superior gap filling properties, ozone-TEOS thermal chemical vapor deposition (CVD) methods typically nonetheless also typically provide shallow trench isolation regions with inferior bulk properties (as typically evidenced by increased aqueous hydrofluoric acid etch rate) and with attenuated deposition rates upon thermal silicon oxide trench liner layers formed employing thermal oxidation of silicon semiconductor substrates within which are formed those shallow trench isolation regions employing those ozone-TEOS thermal chemical vapor deposition (CVD) methods.
As an alternate dielectric layer deposition method which may be employed for forming shallow trench isolation regions when employing shallow trench isolation (STI) methods within semiconductor integrated circuit microelectronics fabrications, high density plasma chemical vapor deposition (HDP-CVD) methods have also recently received considerable attention. High density plasma chemical vapor deposition (HDP-CVD) methods are known as simultaneous sputter and chemical vapor deposition (CVD) methods and they are generally characterized by simultaneously employing a bias sputtering and chemical vapor deposition (CVD) of a trench fill dielectric layer when forming the trench fill dielectric layer into an isolation trench. The high density plasma chemical vapor deposited (HDP-CVD) trench fill dielectric layer is typically subsequently chemical mechanical polish (CMP) planarized to form a patterned planarized shallow trench isolation region within the shallow isolation trench.
While, similarly with ozone-TEOS thermal chemical vapor deposition (CVD) methods, high density plasma chemical vapor deposition (HDP-CVD) methods also form shallow trench isolation regions with enhanced gap filling properties, high density plasma chemical vapor deposition (HDP-CVD) methods also advantageously form shallow trench isolation regions with enhanced physical properties and with increased deposition rates upon thermal silicon oxide layers formed through thermal oxidation of silicon substrate layers. Unfortunately, when forming a patterned planarized shallow trench isolation region employing a chemical mechanical polish (CMP) planarizing of a blanket trench fill dielectric layer formed employing a high density plasma chemical vapor deposition (HDP-CVD) method there is often observed damage to a substrate within which is formed the chemical mechanical polish (CMP) patterned planarized shallow trench isolation region. A pair of schematic cross-sectional diagrams illustrating such substrate damage is shown in FIG. 1 and FIG. 2.
Shown in FIG. 1 is a substrate 20 having formed therein a series of comparatively narrow mesas 21a, 21b and 21c having interposed therebetween a pair of comparatively narrow trenches 22a and 22b, where the series of narrow mesas 21a, 21b and 21c is separated from a comparatively wide mesa 23 by a comparatively wide trench 24. Formed upon the substrate 20 and filling at least the pair of narrow trenches 22a and 22b and the wide trench 24 is a blanket trench fill layer 26 formed employing a high density plasma chemical vapor deposition (HDPCVD) method. As is characteristic for blanket trench fill layers formed employing high density plasma chemical vapor deposition (HDP-CVD) methods, the blanket trench fill layer 26 may be formed to planarize each of the pair of narrow trenches 22a and 22b, along with the wide trench 24, while simultaneously being formed to a greater thickness upon the wide mesa 23 than upon each narrow mesa within the series of the narrow mesas 21a, 21b and 21c.
Referring now to FIG. 2, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1. Shown in FIG. 2 is a schematic cross-sectional diagram of a microelectronics fabrication otherwise equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein the blanket trench fill layer 26 has been chemical mechanical polish (CMP) planarized to form the patterned planarized trench fill layers 26a, 26b, 26c, 26d and 26e, while employing a chemical mechanical polish (CMP) planarizing method as is conventional in the art of microelectronics fabrication. As is illustrated within the schematic cross-sectional diagram of FIG. 2, upon chemical mechanical polish (CMP) planarizing of the blanket trench fill layer 26 to form the patterned planarized trench fill layers 26a, 26b, 26c, 26d and 26e, the narrow mesas 21a, 21b and 21b, but typically not the wide mesa 23, sustain damage as evidenced by erosion in forming the eroded narrow mesas 21a', 21b'and 21c'.
Damaged mesas, such as the eroded narrow mesas 21a', 21b' and 21c', are undesirable within the art of microelectronics fabrication, since it is often difficult to form either fully functional or fully reliable integrated circuit devices or integrated circuits when employing those damaged mesas.
It is thus towards the goal of forming within isolation trenches within semiconductor substrates within semiconductor integrated circuit microelectronics fabrications chemical mechanical polish (CMP) planarized trench isolation regions formed employing high density plasma chemical vapor deposition (HDP-CVD) methods, while simultaneously avoiding semiconductor substrate damage, that the present invention is more specifically directed. In a more general sense, the present invention is also directed towards forming within trenches within substrates employed within microelectronics fabrications which are not necessarily semiconductor integrated circuit microelectronics fabrications chemical mechanical polish (CMP) planarized trench fill layers formed employing high density plasma chemical vapor deposition (HDP-CVD) methods, while simultaneously avoiding substrate damage, that the present invention is more generally directed.
Various methods for forming trench isolation regions for use within isolation trenches within semiconductor substrates within semiconductor integrated circuit microelectronics fabrications have been disclosed within the art of semiconductor integrated circuit microelectronics fabrication.
For example, Pierce et al., in U.S. Pat. No. 5,094,972, disclose a chemical mechanical polish (CMP) planarizing method employing a planarizing stop layer for forming an isolation region within an isolation trench within a semiconductor substrate within a semiconductor integrated circuit microelectronics fabrication. The method may be employed for forming is isolation regions of width as wide as about one millimeter.
In addition, Sato, in U.S. Pat. No. 5,182,221, discloses a bias electron cyclotron resonance chemical vapor deposition (ECR-CVD) method for forming within a microelectronics fabrication a flat and void free isolation region. The method forms the isolation region while employing a vertical:horizontal deposition rate ratio which is equal to two times the depth of an isolation trench to be filled with the isolation region divided by the width of the isolation trench to be filled with the isolation region.
Further, Kwon et al., in U.S. Pat. No. 5,665,635, disclose a method for forming within a semiconductor integrated circuit microelectronics fabrication narrow isolation regions within narrow trenches simultaneously with wide isolation regions within wide trenches while forming the narrow isolation regions and wide isolation regions with enhanced planarity. The method employs a surface treatment of the semiconductor integrated circuit microelectronics fabrication in a fashion such that a dielectric material from which is formed the narrow isolation regions and the wide isolation regions is deposited more rapidly within the narrow trenches and wide trenches than upon areas adjoining the narrow trenches and wide trenches.
Yet further, Jang et al., in U.S. Pat. No. 5,702,977, disclose a method for forming a trench fill layer, such as an isolation region, within a shallow trench, such as an isolation trench, within a semiconductor integrated circuit microelectronics fabrication. Analogously with Kwon et alt. the method employs forming within the shallow trench an integrated circuit layer upon which may be deposited a blanket trench fill layer with a higher growth rate than upon portions of the semiconductor integrated circuit substrate other than those within the trench, but wherein the blanket trench fill layer so formed is formed to a thickness such that when chemical mechanical polish (CMP) planarized there is avoided formation of a dish within a planarized trench fill layer formed within the trench.
Finally, Park et al., in "Stress Minimization in Deep Sub-Micron Full CMOS Devices by Using an Optimized Combination of the Trench Filling CVD Oxides," IEDM 97, IEEE (1997), pp. 669-72, disclose a stress attenuated shallow trench isolation region and method for fabrication thereof for use within a semiconductor integrated circuit microelectronics fabrication. The method employs a first silicon oxide layer formed into an isolation trench employing an ozone-TEOS thermal chemical vapor deposition (CVD) method and a second silicon oxide layer formed thereupon employing a plasma enhanced chemical vapor deposition (PECVD) method.
Desirable in the art of microelectronics fabrication are methods for forming within trenches within substrates employed within microelectronics fabrications which are not necessarily semiconductor integrated circuit microelectronics fabrications chemical mechanical polish (CMP) planarized trench fill layers formed employing high density plasma chemical vapor deposition (HDP-CVD) methods, while simultaneously attenuating substrate damage. More particularly desirable in the art of microelectronics fabrication are methods for forming within isolation trenches within semiconductor substrates within semiconductor integrated circuit microelectronics fabrications chemical mechanical polish (CMP) planarized trench isolation regions formed employing high density plasma chemical vapor deposition (HDP-CVD) methods, while simultaneously attenuating semiconductor substrate damage.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.